Systems that provide physical security of sensitive data such as cryptographic keys typically require enclosures that contain the circuitry that stores and processes the sensitive data. U.S. Pat. No. 4,860,351—‘Tamper Resistance Packaging Protection of Information Stored in Electronic Circuitry’ describes how such a secure enclosure is implemented and is hereby incorporated in its entirety herein. The tamper response to penetration of physical enclosures must remove sensitive data within a period of time that makes breach of the enclosure and data retrieval or data preservation in memory devices highly unlikely. SRAM memory technology is frequently used for memory applications that store sensitive data in security modules. SRAM data remains stored in the memory device as long as power is applied to the device (volatile memory) and the data is not purposely over written using write enable signals. This volatile memory device is used to store sensitive data in secure enclosures because the sensitive data in the entire memory can be destroyed in a relatively fast operation by removing power to the device when a tamper event occurs. The power to the SRAM memory is also backed up with a battery source as there is a requirement to retain certain security data in the security module when the security module is not powered by system power.
When the memory device or security module is subjected to low temperatures the electrical discharge (data destruction) of the memory cell upon power removal or grounding of the power supply takes longer. If some charge still remains on the memory cells when the device is repowered, the memory cells will come up in the same state as before the power was removed. In this ease data previously stored in the memory will be retained. Significant data retention time increases have been observed at lower temperatures but at temperatures still within environmental ranges.
Low temperature attacks try to take advantage of the increased data retention lime to breach the enclosure and repower the memory device before the memory data is destroyed from the tamper response (power removal to the memory device) caused by the enclosure breach.
Conversely, subjecting the memory device to higher voltage than the maximum specified operating voltage of the device for extended periods and/or subjecting the device to higher temperatures for long periods can cause preferential states to be ‘burned into’ the memory storage elements devices. In this scenario memory devices that store data that is not overwritten for long periods of time such as cryptographic keys, could reveal this long term data when first powered up before any initial write operations. Therefore the tamper response becomes ineffective because the removal of power to the memory device may not affect the preferred states within the memory device that will be revealed when powered up.
In light of the above, low temperature attacks that could increase retention time of data in memory technology and high temperature/high voltage attacks that could ‘burn in’ preferred states in memory must be considered in designing the security of the enclosure and enclosed hardware. To address these exposures, temperature and voltage min/max tamper limits can be used to invoke a tamper response if the enclosure and memory device are subjected to temperature extremes. However, temperature and voltage limit thresholds are difficult to determine based on technology retention/burn-in sensitivity. For example different memory technology from different memory suppliers may have longer or shorter retention time sensitivities to lower temperatures and as technology evolves sensitivities of retention time to lower temperatures may change. Such voltage and temperature setting limits also create handling (Electrostatic discharge), shipping, and product storage limitations. For Example, during shipment cargo holds in planes can reach sub 0 Farenheight temperatures and warehouse temperatures may reach well over 100 degrees F. Therefore, if in order to protect against data retention times temperature tamper limit needs to be higher or lower than the temperature the device is exposed to during shipment, special thermal provisions must be made for shipment of the security product. Additionally, with voltage tamper limits, care must be taken to insulate all parts of the security module from accidentally shorting the power distribution system of the module so that an accidental voltage tamper cannot occur due to handling of the security module under battery back up power.
Actively erasing memory using the write function or write enable of the memory provides a more reliable destruction of data than removing power and is not sensitive to the data retention problem. However, in a large memory typical of the sizes needed for the storage of secure data writing over every memory location to be sure all sensitive data is destroyed (active erasure) cannot be completed within the time constraint of a tamper response.
Continuously inverting the memory storage bit locations (changing a 2 state element from 1 state to the other) at a 50% duty cycle to prevent imprinting of a preferred state will prevent the ‘data imprinting’ or ‘burn in’ of the memory cells of the SRAM device, however, it is also difficult and time consuming to implement constant inverting of data in a large memory due to it's size, and the power consumed by a constant switching factor.
To summarize, typical tamper responses to destroy sensitive data trigger off of penetration sensing and temperature/voltage sensing limits, and respond with power removal to SRAM memory to destroy sensitive data. As previously discussed, the quality and time required of this data erasure response can be influenced by temperature and voltage extremes. This invention offers better protection from breaches of the secure enclosure when temperature and voltage extremes (attacks) are used to preserve data retention (time) than only power removal (or grounding of the power terminal) to the memory device.